(1) Field of the Invention
The present invention relates to a method for plasma treating a silicon nitride (Si.sub.3 N.sub.4) passivation layer over closely spaced metal interconnections for integrated circuits on semiconductor substrates, and more particularly relates to a method for eliminating trapped photoresist in the voids (keyholes) that would otherwise outgas during the next level of metal deposition causing metal corrosion. The method also increases the densification of the Si.sub.3 N.sub.4 layer thereby reducing the number of pinholes in the Si.sub.3 N.sub.4 layer that can cause interlevel shorts.
(2) Description of the Prior Art
Multilevels of metal interconnections are used on Ultra Large Scale Integration (ULSI) integrated circuits to wire-up the discrete semiconductor devices on the semi-conductor chips. The different levels of interconnections are separated by layers of insulating material, such as plasma-enhanced chemical vapor deposited (PECVD) silicon oxide and silicon nitride layers. The silicon nitride layers also serve as passivation layers to prevent contamination, for example by light ions such as sodium, that would otherwise degrade the electrical properties of the underlying semiconductor devices. Typically the insulation and passivation layers require low temperature deposition processing (&lt;400.degree. C.) because the metal lines which are usually formed from Al/Cu alloys have a low melting temperature (about 660.degree. C.).
Unfortunately, as the metal lines that form the interconnections are made closer together to satisfy the higher packing density for ULSI integrated circuits, the aspect ratio (the width of the spacings between metal lines to the metal thickness) increases. This results in the formation of voids (keyholes) in the nonconformal insulating or passivation layer that is deposited next. These voids are particularly prevalent when the passivation layer, usually a silicon nitride, is deposited at low temperatures by PECVD resulting in the nonconformal layer.
The void formation or keyhole problem is best understood with reference to FIGS. 1 and 2. Referring to FIG. 1, a schematic cross-sectional view of a portion of the substrate 18 is shown having two closely spaced inter-connecting metal lines 20. Over the metal lines 20 is first deposited a thin PECVD silicon oxide layer 22 that acts as a stress-release layer for the Si.sub.3 N.sub.4 layer 24 which is deposited next. As is depicted in FIG. 1, the deposition flux of the deposited Si.sub.3 N.sub.4 layer is higher at the top corners of the closely spaced metal lines than in the recess between them. This results in the formation of voids 34 having a keyhole shape. When the next photoresist layer 26 is deposited and patterned to form the via hole 3 elsewhere on the substrate 18, residual photoresist can be trapped in the voids 34 under the region 30 in the Si.sub.3 N.sub.4 layer 24. The incomplete removal of the residual photoresist then results in contamination and corrosion of the subsequent metal layer when the trapped photoresist outgases during the subsequent metal deposition step. This can be a serious problem, for example when the via holes are etched to second level metal lines (M2) for the pad metal electrical contacts on dynamic random access memory (DRAM) chips. One way the photoresist can be trapped is depicted in the schematic top view of FIG. 2 of metal lines 20 having the Si.sub.3 N.sub.4 layer 24 thereon. When the photoresist is applied in liquid form by spin coating, the photoresist can enter at the openings 32 at the corners of the metal lines 20. Subsequently, after etching the via holes and removing the photoresist and depositing the next metal layer, the trapped photoresist in the voids 34 (FIG. 1) can outgas or blow-out photoresist along the seam 30 in the passivation layer 24. This results in corrosion of the next metal layer and further can cause reliability problems. Another problem with low-temperature PECVD processing is the porosity of the passivation layer 24 which is also more susceptible to pinhole formation that can result in penetration of mobile ions leading to metal-to-metal shorts.
One method for depositing a passivation layer is described by Ito et al. in U.S. Pat. No. 5,554,418, in which a CVD silicon oxide is deposited on a substrate composed of a resinous or plastic material, and teaches a method of depositing oxide without attacking the underlying substrate. However, Ito does not teach a method of eliminating the problem associated with keyholes as described above.
Another method for depositing thin metal nitride layers is described by Akahori et al., U.S. Pat. No. 5,296,404, but also does not address the keyhole problem.
Therefore, there is still a need to improve the silicon nitride passivation layer over closely spaced metal lines by avoiding photoresist outgassing from voids (keyholes) and by reducing pinhole in the passivation layer that can cause electrical shorts.